1. Field of the Invention
The present invention relates to a phase locked loop (PLL) oscillator circuit, and more particularly relates to a PLL oscillator circuit that detects an unlock state, while automatically retrying relock.
2. Description of the Related Art
[Prior Art]
A PLL oscillator circuit feed-back controls an oscillator in a loop for oscillation so as to keep a constant phase difference between the output from the oscillator and an externally input reference signal.
The PLL oscillator circuit can output a stable oscillatory frequency and is applied to electronic equipment and communication equipment.
[Conventional PLL Oscillator Circuit: FIG. 5]
The following describes a conventional PLL oscillator circuit, with reference to FIG. 5. FIG. 5 is a block diagram exemplifying the configuration of a typical PLL oscillator circuit.
As illustrated in FIG. 5, the PLL oscillator circuit includes: a phase comparator 32 that compares a 1/N divided signal with reference to an external reference signal (F ref) to output a phase differential signal; a charge pump 33 that outputs the phase difference with a voltage of a corresponding pulse width; a loop filter 34 that smoothes the output voltage from the charge pump 33; a voltage controlled crystal oscillator (VCXO) 35 that oscillates and outputs a desired frequency (internal reference signal: output frequency) by regulating the frequency in accordance with the control voltage from the loop filter 34; and a divider 36 that divides the output (internal reference signal) from the VCXO 35 into 1/N.
The output signal has the frequency of N×F ref.
The PLL oscillator circuit operates to feed-back controls the internal VCXO 35 so that a phase difference between the externally input reference signal and the internal VCXO 35 is kept constant, thus obtaining the output of the oscillator locked with the reference signal.
More specifically, the phase comparator 32 compares the phase of the output signal from the VCXO 35 subjected to frequency control by the input voltage with a relatively stable external reference signal and feeds back a DC voltage obtained by smoothing the phase comparison result to the VCXO 35 for PLL control, so as to generate a signal with high precision.
[Related Art]
Related art includes: Japanese Patent Application Laid-Open No. H05-072244 “Phase locked loop (PLL) performance tester” (Applicant: Matsushita Electric Ind Co Ltd/Patent Document 1), Japanese Patent Application Laid-Open No. H09-023154 “PLL circuit” (Applicant: Fujitsu General Ltd/Patent Document 2), Japanese Patent Application Laid-Open No. H10-173520 “PLL circuit” (Applicant: Kawasaki Steel Co/Patent Document 3), Japanese Patent Application Laid-Open No. 2001-183423 “Semiconductor integrated circuit” (Applicant: NEC IC Microcomputer System, Ltd/Patent Document 4), and Japanese Translation of PCT International Application Publication No. 2004-511993 (WO 02/33433) “Built-in self-test circuitry for testing a phase locked loop circuit” (Applicant: Koninklijke Philips Electronics N.V./Patent Document 5).
Patent Document 1 discloses a PLL performance tester that generates a test signal to measure a pull-in range and a lock range while changing the frequency thereof and determines a lock state from the generated test signal and a feedback signal from a PLL so as to detect the frequency of the test signal at the time of change between a lock state and an unlock state.
Patent Document 2 discloses a PLL circuit that compares a plurality of VCO control voltages for locking, determines the control direction of a factor of a factor multiplier to output a direction determination signal, and switches between up and down of the factor in accordance with an unlock detection signal and the direction determination signal to decide a factor.
Patent Document 3 discloses a PLL circuit that controls a reset signal to discharge at least one of an error signal and a control signal.
Patent Document 4 discloses a semiconductor integrated circuit that outputs an enable signal to a BIST circuit storing test result data so as to start a test based on a real operating speed corresponding to a phase lock time of an PLL circuit provided therewith.
Patent Document 5 discloses a self-test circuitry, in which a ratio of a multiplier for each frequency multiplier to a divider of its corresponding divide-by-counter in a frequency divider is a constant value for all frequency multipliers and corresponding divide-by-counters, and when a frequency multiplier among the plurality of frequency multipliers is selected, a multiplexer selects its corresponding divide-by-counter to produce a test output clock.    Patent Document 1: Japanese Patent Application Laid-Open No. H05-072244    Patent Document 2: Japanese Patent Application Laid-Open No. H09-023154    Patent Document 3: Japanese Patent Application Laid-Open No. H10-173520    Patent Document 4: Japanese Patent Application Laid-Open No. 2001-183423    Patent Document 5: Japanese Translation of PCT International Application Publication No. 2004-511993